A particular type of capacitor design is a Metal-Insulator-Metal (MIM) capacitor. MIM Capacitor devices are pervasively used in all modern day electronic devices, and in particular radio frequency and analogue circuitry. MOS capacitor structures are an integral part of MOS Field-Effect Transistors (MOSFETs) used extensively in digital circuitry. Portable consumer and communication devices are driving miniaturisation of these devices along with ultra lower power consumption requirements to extend battery life.
Miniaturisation of digital components has centred on the scaling of MOSFET devices, and this has been achieved so far with the introduction of metal gate/high-k/Si MOS structures. Nevertheless, future scaling will likely require the replacement of Si with a higher mobility semiconductor like Ge and/or In0.53Ga0.47As in combination with alternative architecture (e.g. trigate MOSFET, junctionless MOSFET, etc.), introducing different problem issues in controlling device performance. One problem with high-k materials is the capacitance hysteresis observed for high-k material systems, causing variability in the electrical characteristics and thereby directly affecting device performance.
Miniaturisation of RF and analog components is a real problem in the electronics industry. Four key requirements of a dielectric in the design of a capacitor device are to: (i) aim for a low frequency capacitance density as high as possible at zero DC bias; (ii) have as low a leakage current density as possible at the device operating voltage to ensure reliable operation; (iii) have as high a breakdown voltage (BV) as possible for a given thickness (Electric Field Breakdown [MV/cm]), preferably at twice the operating voltage; and (iv) have negligible charge trapping (negligible Capacitance-Voltage hysteresis).
The behaviour of capacitance with applied DC bias is measured using (Cmax−Cmin)/Cmin=Cdif=αV2+βV+c, where Cmin is the minimum measured capacitance, Cmax is the capacitance at the maximum applied voltage, α is the quadratic voltage coefficient of capacitance, β is the linear voltage coefficient of capacitance, and c is a constant accounting for any asymmetry in capacitance about 0V.
If α were approximately ≦|50-100| ppm/V2, the capacitor would exhibit approximate linear rather than quadratic behaviour with voltage, showing a slope determined by α, since β can be reduced to zero by circuit design methods, hence α is the determining factor whether capacitance varies with applied voltage. Units for measuring α are ppm/V2 when β=0; but when β≠0 then the units for measuring β are ppm/V, since Cdif, α, and β are constants.
An additional requirement for many capacitor applications is that the capacitor exhibit linear capacitance behaviour with respect to the applied voltage, as a large non-linearity creates detrimental harmonics in electronic circuits, especially at high frequencies, as well as other non-ideal effects. A measure of this linearity is α, since β and c can be made to equal zero through careful circuit and device design.
For these same applications, capacitance should also remain linear as the temperature and frequency change: α(Tmax)−α(Tmin)≦|100| units/K, and α(Fmax)−α(Fmin)≦1% units per decade, respectively. There are also many capacitor applications for which this linearity of capacitance with voltage, temperature, and frequency is not required. To date, for a given relative permittivity (k) and oxide thickness (t), higher capacitance has been achieved by using larger area capacitors, since C=kε0A/t, where C is capacitance, ε0 is a constant (the permittivity of free space), and A is the area of the capacitor. The requirement of large area for the capacitors prevents any significant reduction in the surface footprint size of analogue circuitry.
Reducing the oxide thickness (t) of the capacitor could in theory achieve the same capacitance (C) for a smaller capacitor area (A) for a given k, but this would detrimentally increase the leakage current and reduce the breakdown voltage of the capacitor.
The ideal solution for surface planar capacitors would be to increase the relative permittivity (k) of the oxide and reduce the area (A) for the same oxide thickness (t) to achieve the same or greater capacitance (C). However, to date this approach has been undermined by the high leakage and low breakdown voltages associated with high-k dielectrics, demonstrating high-k MIM devices but with unacceptable leakage and breakdown characteristics. Such structures also generally exhibit a high a value. Some high-k materials require annealing to achieve the highest k-value, and this can also contribute to higher leakage and lower breakdown voltages.
In addition, high-k materials are generally ionic systems and tend to have a significant density of charge trapping sites and therefore a significant hysteresis, which can be improved by selective deposition techniques, processing, and annealing but not entirely removed. Charge trapping, and the associated electrical variability, remain serious problems for high-k dielectrics.
Present MIM capacitors with control of a and hysteresis rely on low k-value and covalently bonded systems such as silicon oxide, silicon nitride, or silicon oxynitride dielectrics (k˜4-6), as these oxides also allow control of the leakage and breakdown characteristics. A maximum capacitance is achieved through the use of large area capacitors. Minimal hysteresis is achieved through careful concentration ratio selections, processing and annealing.
Increased capacitance with reduced surface area can be achieve through stacking capacitors on top of each other in a 2-dimensional way and connecting in parallel. If the number of dielectric layers is n, then C=n×kε0A/t, and the same capacitance can be achieved with reduced area. In reality there is a limit to the number of layers achievable due to processing constraints on conformal growth and connectivity requirements, and typical values of n are ≦4. MIM capacitors with high-k materials can also be made in this way permitting further scaling.
Another way to increase capacitance is by making 3-dimensional MIM capacitors inside trenches etched into silicon and surface treated to obtain an SiO2 isolation layer. Conformal growth methods could then be used to grow single or stacked layers of metal-insulator-metal structures. This method permits the possibility of the area being increased to as large as possible alongside n and k in C=n×kε0A/t. For this scenario it is the capacitor footprint on the surface that is minimised, not the device area. In reality, most deposition methods in industry have serious constrictive difficulties in making these type of capacitors. MIM capacitors with high-k materials can also be made in this way using conformal growth methods, permitting further scaling.
US patent publication number US 2006 0281264 A1, assigned to Matsushita Electric Industrial Co. Ltd., describes a gate insulator on a semiconductor substrate having a plurality of oxide layers perpendicular to the semiconductor surface and associated with respective phases.
The US patent publication discloses three stable layers formed from the ALD|CVD of SiO2, MSiO4, and MO2 stable phases (M=Hf|Zr). However, problems with this approach are: (i) that an unstable interface is formed between the SiO2 layer and the claimed MSiO4 layer; (ii) the thickness of the amorphous SiO2 layer increasing with time taking SiO2 from the claimed MSiO4 layer; and (iii) the claimed MSiO4 layer actually moves increasingly towards a crystalline MO2 concentration with time. Namely, the claimed MSiO4 layer will reduce in SiO2 concentration with time, and exhibit spontaneous phase separation to form amorphous SiO2 and crystalline MO2 (MxSi1-xO2, x=0.5→x=1.0) with time.
The deposition of a higher x concentration MxSi1-xO2 (M=Hf|Zr, x>0.5) will ensure a nucleation and growth phase separating structure due to two factors: (i) the deposited oxide (from bulk theory) will be intrinsically metastable at such x concentrations (not stable), and (ii) the oxide is deposited on SiO2 ensuring the growth of SiO2 from Si and O supplied by the decomposition of the MxSi1-xO2 oxide.
Hence, phase separation is driven by the unstable bottom interface with amorphous SiO2, the bulk phase separation and forming of amorphous SiO2 and crystalline MO2 clusters, and the changing x concentration to form amorphous SiO2 and crystalline MO2 (MxSi1-xO2, x>0.5→x=1.0) with time.
It is clear that a MIM or MOS capacitor exhibiting such a structure of three stable phases claimed of SiO2, MSiO4, and MO2 is neither stable with time nor free from crystalline grain boundaries that would cause high operating voltage leakage current densities and a low breakdown field.
To date the research and development community have only been able to synthesis amorphous or polycrystalline MxSi1-xO2 metal silicates (0<x<1; M=Zr and/or Hf), which can be synthesised fairly easily. If synthesised films form amorphous systems, including the amorphous forms of zircon and hafnon, and they are exposed to a high enough temperature anneal in an appropriate ambient, they can be made polycrystalline.
However, the amorphous to crystalline transition does not form a single crystal for any significantly large crystallite length scale, but instead forms many small crystals all oriented in different directions with crystallite sizes very much smaller than the thickness of the films. The boundaries between these crystallite regions, called grain boundaries, render these dielectric films effectively useless for electronics applications due to the very high leakage and low breakdown voltages associated with such grain boundary rich films.
A paper publication by Ting-Ting Jiang et al., J. Phys. D: Appl. Phys. 44, 185402, 1-5 (2011) a theoretical simulation which tries to compare the electronic band gaps modelled and experimental amorphous high-k materials that could be used in a semiconductor device. However Ting-Ting Jiang does not demonstrate any type of device characteristics. The device properties referred to in the introduction section of the Ting-Ting Jiang et al. paper, with respect to the ZrSiO4 and HfSiO4 systems, are for amorphous systems only. Moreover modelling programs are not able to model amorphous systems because of their size and complexity. Geological studies of crystallites in naturally formed rock give lattice parameters for modelling crystalline systems, and these geological studies are the experimental results referred to in the paper for the unit cells used in the simulations. To date no one has been able to reproduce these materials for use in electronic devices and the prior art relates to purely amorphous or polycrystalline materials that are limited for electronic devices.
Another publication by T. S. Böscke et al., Appl. Phys. Lett. 91, 072902 (2007) reports on HfO2 and the addition of 10% SiO2 to form an amorphous Hf0.9Si0.1O2 metal silicate (x=0.9, M=Hf). The T. S. Böscke et al. paper claims that crystallisation of amorphous HfO2 into the monoclinic form of HfO2 after a thermal anneal leads to increased leakage and the formation of local defects. By adding 10% SiO2 to the amorphous HfO2, T. S. Böscke et al claim that tetragonal HfO2 is formed instead of monoclinic HfO2 during the thermal anneal process. Doping amorphous HfO2 with 10% SiO2 and crystallising with a temperature anneal does not constitute the formation of amorphous, or polycrystalline HfSiO4 (x=0.5) but the formation of Hf0.9Si0.1O2 (x=0.9).
A further paper by K. Kukli et al., Material Science and Engineering B 109 (1-3), 2-5 (2004) reports experimental findings for two types of substrate layers on which they deposit their oxide:                I. Si/SiO2 (1.2-1.8 nm)        II. Si (chemically etched, nominally Si—H)        
The paper refers to Hf—Si—O which has a 2:1 Hf:Si concentration ratio (x˜0.67) and is amorphous, and as such due to x and the amorphous properties of the material suffers from the same drawbacks as described above.
A further publication by Lizhi Ouyang and W. Y. Ching, J. Appl. Phys. 95 (12), 7918-7924 (2004) discloses a modelling paper similar to the Ting-Ting Jiang paper and simulates (ZrO2)x(SiO2)1-x with x<0.5. Again the simulations use the lattice parameters from geological studies of crystallites in rock and then substitute Zr with Si cations to get x<0.5. The experimental comparison they refer to for ZrSiO4 or zircon is from experiment XPS studies on powders with x=0.5 but in an amorphous or polycrystalline state.
An object of the invention is to provide a stable oxide material system for a capacitor or electronic device having an effective high-k value with an effective zero alpha while exhibiting low leakage current density and a high electrical breakdown field.